大规模并行处理器程序设计 影印本 英文版

1 (p1): CHAPTER 1 INTRODUCTION
2 (p2): 1.1 GPUs as Parallel Computers
8 (p3): 1.2 Architecture of a Modern GPU
10 (p4): 1.3 Why More Speed or Parallelism?
13 (p5): 1.4 Parallel Programming Languages and Models
15 (p6): 1.5 Overarching Goals
16 (p7): 1.6 Organization of the Book
21 (p8): CHAPTER 2 HISTORY OF GPU COMPUTING
21 (p9): 2.1 Evolution of Graphics Pipelines
22 (p10): 2.1.1 The Era of Fixed-Function Graphics Pipelines
26 (p11): 2.1.2 Evolution of Programmable Real-Time Graphics
29 (p12): 2.1.3 Unified Graphics and Computing Processors
31 (p13): 2.1.4 GPGPU:An Intermediate Step
32 (p14): 2.2 GPU Computing
33 (p15): 2.2.1 Scalable GPUs
34 (p16): 2.2.2 Recent Developments
34 (p17): 2.3 Future Trends
39 (p18): CHAPTER 3 INTRODUCTION TO CUDA
39 (p19): 3.1 Data Parallelism
41 (p20): 3.2 CUDA Program Structure
42 (p21): 3.3 A Matrix-Matrix Multiplication Example
46 (p22): 3.4 Device Memories and Data Transfer
51 (p23): 3.5 Kernel Functions and Threading
56 (p24): 3.6 Summary
56 (p25): 3.6.1 Function declarations
56 (p26): 3.6.2 Kernel launch
56 (p27): 3.6.3 Predefined variables
57 (p28): 3.6.4 Runtime API
59 (p29): CHAPTER 4 CUDA THREADS
59 (p30): 4.1 CUDA Thread Organization
64 (p31): 4.2 Using blockIdx and threadIdx
68 (p32): 4.3 Synchronization and Transparent Scalability
70 (p33): 4.4 Thread Assignment
71 (p34): 4.5 Thread Scheduling and Latency Tolerance
74 (p35): 4.6 Summary
74 (p36): 4.7 Exercises
77 (p37): CHAPTER 5 CUDATM MEMORIES
78 (p38): 5.1 Importance of Memory Access Efficiency
79 (p39): 5.2 CUDA Device Memory Types
83 (p40): 5.3 A Strategy for Reducing Global Memory Traffic
90 (p41): 5.4 Memory as a Limiting Factor to Parallelism
92 (p42): 5.5 Summary
93 (p43): 5.6 Exercises
95 (p44): CHAPTER 6 PERFORMANCE CONSIDERATIONS
96 (p45): 6.1 More on Thread Execution
103 (p46): 6.2 Global Memory Bandwidth
111 (p47): 6.3 Dynamic Partitioning of SM Resources
113 (p48): 6.4 Data Prefetching
115 (p49): 6.5 Instruction Mix
116 (p50): 6.6 Thread Granularity
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