Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
Takayasu Sakurai, Akira Matsuzawa, Takakuni Douseki
The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V.
Categories:
Year:
2010
Edition:
1st Edition.
Publisher:
Springer
Language:
english
Pages:
420
ISBN 10:
1441939776
ISBN 13:
9781441939777
File:
PDF, 10.35 MB
IPFS:
,
english, 2010